Field of the Invention
Embodiments of the present invention relate to managing timing in electronic circuits, and more particularly, to design and implementation of a Duty Cycle Correction Circuit (DCCC), thereby facilitating correcting the duty cycle of a clock signal and outputting a clock signal with a corrected duty cycle.
Description of the Related Art
Electronic systems are often implemented in a micro-electronic circuit typically referred to as an Integrated Circuit (IC). The electronic systems typically include a number of passive and active electronic components, including but not limited to, transistors, resistors, capacitors, inductors, logic gates, linear amplifiers, voltage regulators, signal processors and converters, and the rest.
Many ICs generate an internal clock signal based on a received clock signal. A number of signal processing, data transfer, and other functions are performed employing the internal clock signal. For example, analog signals are converted into the digital domain, complicated signal processing functions are performed; digital signals are stored, high speed data transfer operations are performed, and the like.
The reliable generation of the internal clock signals is an important aspect of IC design, especially with increasing clock frequencies. Compensation of external and internal non-ideal characteristics of the received and generated clock signals prevent operating inefficiencies and other complications in electronic systems.
As many clock driven digital systems are required to perform at higher speeds, designers are investigating different options to achieve the high speed operation. Designers may decide to use both the rising and the falling edge of a given clock signal to double the total number of operations. However, the usage of both the rising and the falling edge of a given clock signal to double the total number of operations requires a clock to output accurate 50% duty-cycle to prevent or reduce jitters and other timing related aberrations.
At relatively low frequencies of clock signals, one method to provide a desired symmetrical clock signal uses a conventional flip-flop circuit to perform an equivalent division-by-two for deriving an output clock signal frequency. As per the aforementioned method, the source clock frequency must be two times faster than the desired circuit design operating frequency. However, as frequencies increase, the source clock frequency will reach the technology limitation before reaching the circuit design operating frequency. Conventional methods or topologies that have been proposed do not generate a very accurate multiply-by-2 output frequency because some of these methods use a digital controller to select a fixed number of delays. In the case of varying duty-cycles, using a fixed number of delays is not effective to generate accurate multiply-by-2 output frequencies.
However, there is still a need for enhanced methods, apparatuses and systems for managing clock Duty Cycle Correction (DCC).